|ELECTRONIC CIRCUITS & LOGIC DESIGN LABORATORY (Common to CSE & ISE)|
|Written by Administrator|
|Sunday, 08 November 2009 11:50|
PART – A
1. a. To study the working of positive clipper, double-ended clipper and positive clamper using diodes.
b. To build and simulate the above circuits using a simulation package
2. a. To determine the frequency response, input impedance, output impedance, and bandwidth of a CE amplifier.
b. To build the CE amplifier circuit using a simulation package and determine the voltage gain for two different values of supply voltage and for two different values of emitter resistance.
3. a. To determine the drain characteristics and transconductance characteristics of an enhancement-mode MOSFET.
b. To implement a CMOS inverter using a simulation package and verify its truthtable.
4. a. To design and implement a Schmitt trigger using Op-Amp for given UTP and LTP values.
b. To implement a Schmitt trigger using Op-Amp using a simulation package for two sets of UTP and LTP values.
5. a. To design and implement a rectangular waveform generator (Op-Amp relaxation oscillator) for given frequency.
b. To implement a rectangular waveform generator (Op-Amp relaxation oscillator) using a simulation package and observe the change in frequency when all resistor values are doubled.
6. To design and implement an astable multivibrator circuit using 555 timer for a given frequency and duty cycle.
7. To implement a +5V regulated power supply using full-wave rectifier and 7805 IC regulator in simulation package. Find the output ripple for different values of load current.
PART – B
1. a. Given any 4-variable logic expression, simplify using Entered Variable Map and realize the simplified logic expression using 8:1 multiplexer IC.
b. Write the Verilog /VHDL code for an 8:1 multiplexer. Simulate and verify its working.
2. a. Realize a full adder using 3-to-8 decoder IC and 4 input NAND gates.
b. Write the Verilog/VHDL code for a full adder. Simulate and verify its working.
3. a. Realize a J-K Master/Slave Flip-Flop using NAND gates and verify its truth table.
b. Write the Verilog/VHDL code for D Flip-Flop with positive-edge triggering. Simulate and verify its working.
4. a. Design and implement a mod-n (n<8) synchronous up counter using J-K Flip-Flop ICs.
b. Write the Verilog/VHDL code for mod-8 up counter. Simulate and verify its working.
5. a. Design and implement a ring counter using 4-bit shift register.
b. Write the Verilog/VHDL code for switched tail counter. Simulate and verify its working.
6. Design and implement an asynchronous counter using decade counter IC to count up from 0 to n (n<=9).
7. Design a 4-bit R-2R ladder D/A converter using Op-Amp. Determine its accuracy and resolution.
Note 1. Any simulation package like MultiSim/Pspice etc. may be used.